The present invention relates, generally, to integrated circuit packaging, and more particularly relates to methods and devices for packaging microelectronic devices.
Microelectronic devices are typically comprised of one or more silicon die/dice having, at least in material part, a multitude of die bond pads on a front surface, a chip body, an interconnection scheme to connect the pads on the die to a supporting substrate and an encapsulant to ensure that the die is protected from contaminants. The combination of these elements is generally referred to as a chip package. The specific function of this package is to protect the die from mechanical, electrostatic and environmental stresses while at the same time providing a thermal path for the heat dissipated from the at least one die during use.
More specifically, chip packages must be able to accommodate for many inherent microelectronic device problems, such as die power dissipation, mismatches in the thermal coefficients of expansion between the chip and its supporting substrate, and increasingly smaller die bond pad pitch, which ultimately allows smaller dies to be used and thus has the potential to produce either smaller packages or more densely packed multi-die packages so long as the interconnection scheme chosen can accommodate the fineness of the pad pitch.
Microelectronic devices are typically connected to external circuitry through contacts on a surface of the chip. The device contacts are generally either disposed in regular grid-like patterns, substantially covering the front surface of the chip (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the chip front surface. The various prior art processes for making the interconnections between such microelectronic devices and their supporting substrates use prefabricated arrays or rows of leads, discrete wires, solder bumps or combinations thereof. For example, in a wirebonding process, the chip may be physically mounted on a supporting substrate. A fine wire is fed through a bonding tool. The tool is brought into engagement with the contact on the chip so as to bond the wire to the contact. The tool is then moved to a connection point of the circuit on the substrate, so that a small piece of wire is dispensed and formed into a lead, and connected to the substrate. This process is repeated for every contact on the chip. The wire bonding process may also be used to connect the die bond pads to lead frame fingers that are then connected to the supporting substrate.
In a tape automated bonding (“TAB”) process, a dielectric supporting tape, such as a thin foil of polyimide is provided with a hole slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the hole towards the edges of the hole. Each lead has an innermost end projecting inwardly, beyond the edge of the hole. The innermost ends of the leads are arranged side by side at spacing corresponding to the spacing of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the hole is aligned with the chip and so that the innermost ends of the leads will extend over the front or contact bearing surface on the chip. The innermost ends of the leads are then bonded to the contacts of the chip, typically using ultrasonic or thermocompression bonding. The outer ends of the leads are connected to external circuitry.
In a “beam lead” process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
More recently, flip chip configurations have been used. In flip chip configurations, a solder ball is deposited on top of each of the chip contacts and then abutted against respective substrate contacts. The solder balls are then reflowed to provide an electrical connection between the chip and the substrate.
The rapid evolution of semiconductor art in recent years has created a continued demand for progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within a very small area and many times within the area of the front surface of the chip package. For example, a complex semiconductor chip package in current practice may have a row of contact pads spaced apart from one another at center-to-center distances of 0.15 mm or less and, in some cases, 0.10 mm or less. These distances are expected to decrease progressively with continued progress in the art of semiconductor fabrication. Wire bonding can currently only accommodate a die pad pitch of approximately 100 pm and TAB bonding allows only a pad pitch or about 70-80 pm. If a smaller pad pitch were possible in production, it would allow the die size to be reduced for “pad limited designs where the die perimeter is required to be large enough to fit all of the bond pads.
Further, with such closely-spaced contacts, the leads connected to the chip contacts, must be extremely fine structures, typically less than 50 pm wide. Such fine structures are susceptible to damage and deformation. With closely spaced contacts, even minor deviation of a lead from its normal position will result in misalignment of the leads and contacts. Thus, a given lead may be out of alignment with the proper contact on the chip or substrate, or else it may be erroneously aligned with an adjacent contact. Either condition can yield a defective chip assembly. Errors of this nature materially reduce the yield of good devices and introduce defects into the product stream. These problems are particularly acute with those chips having relatively fine contact spacing and small distances between adjacent contacts.
Many of the prior art techniques for attachment further run into problems because of the thermal expansion mismatch between the material comprising the microelectronic device and the material comprising the supporting substrate. In other words, when heat is applied to the microelectronic device/substrate combination, they both expand; and when the heat is removed, the device and the substrate both contract The problem that arises is that the device and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. This directly affects the reliability of these connection schemes.
It has been proposed to provide a pressure clamped TAB structure where the outer leads have bumps which can be pressure clamped to respective contacts on the supporting substrate. A compliant pad is then placed over the TAB leads to help hold each of the bumps into electrical contact with corresponding lead contacts on the substrate. However, the compliant pad will eventually take a permanent set, thereby reducing the reliability of the contact force over time. An alternate TAB solution put forth involves replacing the outer lead bond pads of the TAB chip carrier, which connects to the substrate, with an area array of solder balls. The die is then connected to the carrier by means of solder bumps, wire bonds, or TAB inner lead bond pads. The problem here is that the solder balls undergo mechanical stress due to differential thermal expansion of the TAB chip carrier relative to the supporting substrate thereby causing cracking of the solder balls reducing their reliability.
Thermal mismatch issues will be more significant as multiple chip modules grow in popularity. Typically, as more dice are packaged together, more heat will be dissipated by each package which, in turn, means the package will expand to a greater extent thereby further stressing the interconnections. Effective package heat dissipation schemes have thus become increasing important. Typical package cooling schemes include heat sinks and small air fans which are applied or affixed to the back side of the chip body, which is further typically made of ceramic or plastic. One problem with these solutions is that the back layer of the chip package body, to varying degrees, acts as a thermal barrier between the die and the thermal cooling device inhibiting good thermal conduction to the exterior surface of the package.
Further, impedance, inductance and capacitance problems begin to seriously degrade a chip package's performance as the pad pitch becomes finer and the clock speed of a chip is increased. Factors such as the length of interconnection wires and the crosstalk between the chip's interconnections also need to be addressed when a chip package is being designed for the same reason.
To be commercially viable, the aforementioned problems must be solved in a manner which respects the small package size, multichip constraints, fine die bond pad pitch, thermal problems, compliancy problems, electrical problems and in addition must be a cost effective IC package.
Thus, despite the substantial time and effort devoted heretofore to the problems associated with mounting and connecting of microelectronic devices, there are still been unmet needs for improvements in such processes and in the equipment and components used to practice them.